The present invention relates to a method for manufacturing a semiconductor integrated circuit device (or semiconductor device), and in particular, a technique useful in applications to semiconductor devices having an SOI structure.
JP-A-10-303385 (Patent Document 1), has disclosed a technique for exposing a silicon substrate in a region constituting a part of the SOI substrate, namely a bulk device region, forming a memory cell region of DRAM (Dynamic Random Access Memory) in the bulk device region, and forming a logic region in a region where the silicon substrate is not exposed, namely SOI device region.
JP-A-2007-184549 (Patent Document 2) has disclosed a technique for burying a device isolation insulative film in parallel with burying an insulative film in a cavity portion to make an underlying oxide film in the case of forming, from a single-crystal silicon substrate or the like, a device having a bulk device region and a device region.
JP-A-2004-47844 (Patent Document 3) has disclosed a technique for exposing a silicon substrate in a bulk device region of a SOI substrate, causing an epitaxial silicon layer to grow in the region, and then forming an STI (Shallow Trench Isolation) region.
WO2001/067509 (Patent Document 4) and U.S. Pat. No. 7,005,755 (Patent Document 5) corresponding thereto have disclosed a technique for forming an alignment mark for superposition of a pattern in a part of an SOI substrate where an SOI layer and a BOX layer are removed.
JP-A-07-211610 (Patent Document 6) has disclosed a technique in forming an alignment mark for superposition of a pattern in an SOI substrate, by which an alignment mark is formed by removing an SOI layer and a BOX layer, and etching an underlying substrate.